Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits

Abstract

Proposes an FPGA-based system to speed-up fault injection campaigns for the evaluation of the fault-tolerant capabilities of VLSI circuits. An environment is described, relying on FPGA-based emulation of the circuit. Suitable techniques are described, allowing one to emulate the effects of faults and to observe faulty behavior. The proposed approach allows the combination of the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that significant speed-up figures with respect to state-of-the-art simulation-based techniques can be achieved.