{"title":"Dynamic Decimal Adder Circuit Design by using the Carry Lookahead","authors":"Y. You, Yong-Dae Kim, J. Choi","doi":"10.1109/DDECS.2006.1649627","DOIUrl":null,"url":null,"abstract":"This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2006.1649627","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns
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