A Cost-Effective Wafer-Level Burn-In Technology

Abstract

A new wafer-level bum-in method is presented. The method incorporates a silicon "bum-in substrate" fabricated using MCM-D substrate technology, and includes integral isolation resistors. The novel, Si wafer-to Si wafer pressure contact technology is based on deformable solder bumps and is functional in a high temperature burn-in environment, immune to thermal expansion mismatch problems, reusable, and does not damage or contaminate bond pads. The method is suitable for high-volume production and can reduce bum-in costs, even for chips that are ultimately destined for single-chip packages.