CMOS capacitor coupling logic (C/sup 3/L) circuits

Abstract

The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C/sup 3/L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified.