A low power, high dynamic range and area efficient cyclic on-chip delay measurement architecture

Abstract

In this paper, a crossover based delay mechanism accompanied with a circular vernier delay line architecture is proposed to measure path delays. Measurement of propagation delays on critical path with an on-chip circuit has the potential of detecting small delay defects even when the integrated circuit is in operation. The new architecture drastically reduces the count of delay stages to achieve a large measurement range without reducing the measurement resolution. It achieves a maximum range of 100ns at 5M samples/s with a resolution of 10ps, while consuming 8.21mW power and has an area of .023mm2 in 180nm CMOS technology.