Synthesis and design of a 7/sup th/ order SC lowpass decimator combining externally cascaded and ladder structures

Abstract

This paper proposes a computer-automated synthesis of SC decimators with a high decimating factor based on the statistical approach of the program (ISCMRATE). This methodology is implemented based on multi-decimation building blocks, such as externally cascaded, internally cascaded or ladder structures and polyphase input networks. The design criteria are given to obtain and evaluate the performance of the corresponding resulting circuits. A design example of a 7/sup th/ order SC lowpass elliptic decimator with M=10 is given to illustrate the above proposed methodology.