Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming

Abstract

Spin-transfer-torque magnetic random access memory (STT-MRAM) shows great potential to replace mainstream working memories thanks to its high energy efficiency and endurance. As RAM-like applications require higher speed, it is preferred to use a robust current-type sense amplifier (SA) with complex operating timing, which limits their working speed. The timing generated by the inverter chain is greatly affected by the process, voltage, and temperature (PVT) variations. In this work, a clock trimming sensing scheme is proposed to increase sensing speed and solve PVT variation in current-type SA. Since the timing is generated through voltage difference sampling between differential inputs, this scheme can achieve stable and fast sensing over a wide temperature range. According to the simulation results, the proposed scheme can sense data within 8-ns (near LLC working speed) and save up to 45.6% of energy consumption compared to the traditional SAs.