Node normalization and decomposition in low power technology mapping

Abstract

In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation. We present a normalization algorithm which extracts the largest nodes of the given netlist. Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes. Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) and uncorrelated signal probabilities.