Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors

B. Hoefflinger, J. Schneider, G. Zimmer
{"title":"Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors","authors":"B. Hoefflinger, J. Schneider, G. Zimmer","doi":"10.1109/IEDM.1977.189225","DOIUrl":null,"url":null,"abstract":"An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.","PeriodicalId":218912,"journal":{"name":"1977 International Electron Devices Meeting","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1977.189225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
先进的兼容N-MOS, CMOS和双极晶体管的LSI工艺
提出了一种先进的大规模集成电路工艺,将高性能、高密度n-MOS增强/耗尽、CMOS和npn双极晶体管集成在同一芯片上,以实现具有模拟和数字功能的片上系统。该过程涉及6个用于结构定义的掩膜和多达3个用于选择性植入物的光刻胶掩膜。兴奋剂只能通过植入来完成。MOS阈值电压的标准差< 100mv,双极电流增益可设置在60 ~ 300之间。源极和漏极以及非活动基极区域的片电阻对于高频性能和高集成度来说是低的。场阈值和击穿电压超过25v。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Anodic oxidation of GaAs in oxygen plasma Life begins at forty: Microwave tubes Multi-anode microchannel arrays Gunn effect high-speed carry finding device for 8-bit binary adder New type of varactor diode having strongly nonlinear C-V characteristics
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1