A differential floating gate capacitance mismatch measurement technique

Abstract

This paper describes a differential floating gate capacitance matching measurement technique that offers a significant improvement in resolution over those previously reported. It's smaller differential output voltage can be measured to a much higher precision than that of a standard structure. In addition, the differential technique offers superior cancellation of parasitic overlap capacitance effects. Our technique was successfully demonstrated on a 0.50 /spl mu/m analog BiCMOS technology.