{"title":"Adder merged DRAM architecture","authors":"M. Hashimoto","doi":"10.1109/MTDT.2002.1029768","DOIUrl":null,"url":null,"abstract":"A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.
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