Bimodal MOS-bipolar monolithic kitchip array

S. Combs, J. Meindl
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引用次数: 1

Abstract

COMBINED FET/BJT TECHNOLOGIES have recently generated increasing interest’ 5’. This paper will describe fully complementary, combined MOS-bipolar technology optimized for use in a monolithic Kitchip array of unconnected transistors, resistors, and MOS capacitors. The need for high performance integrated circuits is often overriden by their development cost and poor potential for volume production. The Kitchip represents a quick, cost-effective means for bringing IC technology to many of these applications. Prefabricated Kitchip ICs may be transformed into virtually any simple digital or linear circuit configuration by using a single customizing aluminum interconnect pattern. The underlying eight masks defining the Kitchip are never altered. Several key features distinguish the Kitchip from available IC arrays. A new process yields two self-aligned, low current optimized bimodal (MOS or bipolar) N and P type transistors, low on-resistance VMOS switches for signal multiplexing, ion-implanted low and high value resistors, and a low voltage JFET. The operational mode of any bimodal transistor is determined only by the metal interconnection pattern. Therefore, micropower CMOS and complementary bipolar logic can be realized simultaneously with high performance MOS or bipolar linear functions on the same chip. Surface aluminum, polysilicon cross-unders, and diffused tunnels provide three levels of interconnection permitting efficient device utilization. Compared to a standard six mask linear process, fabrication of the Kitchip requires an additional ion-implant, polysilicon deposition and an anisotropic etch. The dual N type bimodal transistor, Figure 1, o erates as either a bipolar NPN or aluminum. gate VMOS transistor . The bimodal transistor features an isolated source and buried layer drain VMOS with channel characteristics determined by a boron (P-) ion implantation and conventional downward diffusion. Additional arsenic (N’) and boron (P’) implants precisely define its NPN beta, fT, and breakdown voltage.
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双峰mos双极单片kitchip阵列
FET/BJT联合技术最近引起了越来越多的兴趣。本文将描述完全互补,结合MOS双极技术优化用于单片Kitchip阵列的未连接晶体管,电阻器和MOS电容器。对高性能集成电路的需求往往被其开发成本和批量生产潜力不足所掩盖。Kitchip代表了将集成电路技术带入许多这些应用的快速,经济高效的手段。预制Kitchip ic可以通过使用单个定制的铝互连模式转换为几乎任何简单的数字或线性电路配置。定义Kitchip的八个面具从未改变。几个关键功能区分Kitchip从现有的IC阵列。新的工艺产生了两个自校准,低电流优化的双峰(MOS或双极)N型和P型晶体管,用于信号复用的低导通电阻VMOS开关,离子注入的低值和高值电阻器以及低压JFET。任何双峰晶体管的工作模式仅由金属互连模式决定。因此,微功耗CMOS和互补双极逻辑可以与高性能MOS或双极线性功能同时在同一芯片上实现。表面铝,多晶硅交叉下,和扩散隧道提供三个层次的互连允许有效的设备利用。与标准的六掩膜线性工艺相比,Kitchip的制造需要额外的离子植入、多晶硅沉积和各向异性蚀刻。双N型双峰晶体管,如图1所示,可作为双极NPN或铝制晶体管工作。栅极VMOS晶体管。该双峰晶体管具有隔离源和埋层漏极VMOS,其通道特性由硼离子注入和常规向下扩散决定。额外的砷(N′)和硼(P′)植入物精确地定义了其NPN β、fT和击穿电压。
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