{"title":"Bridging the testing speed gap: design for delay testability","authors":"H. Speek, H. Kerkhoff, M. Sachdev, M. Shashaani","doi":"10.1109/ETW.2000.873771","DOIUrl":null,"url":null,"abstract":"The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE European Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETW.2000.873771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed.
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