A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module

Abstract

Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging non-volatile memory and is regarded as a next generation memory. Efforts have been made in its write scheme, but the proposed schemes suffer from high write power and reliability issues. In this paper, we propose a low-power high-reliability write scheme with real-time voltage sensing and control module. Write operations are immediately terminated when the states of cells switch as desire, and when the current state match the state to be switched into, write operations will be terminated directly. The scheme is implemented and simulated in SMIC 40nm Logic Low Leakage process. Simulation results show that write power is 0.106pJ/bit on average, which is 62.5% less than the traditional scheme, and the effective judgment range of write “0” and write “1” is 408mV and 275mV respectively which is 3.15 times larger than the best previously result to our knowledge to reach high write reliability.