A 360μW Vernier Time-to-Digital Converter for ADPLL in IoT Applications

Abstract

An improved Vernier time-to-digital converter (TDC) with overflow bits is designed for low power applications. The overflow bits are added to the Vernier-TDC to reduce the stages of the TDC, thus saving power. A digital-to-time convertor is employed to realize the fractional division and reduce the stages of TDC. Fabricated in 55-nm CMOS, TDC together with DTC consumes only 360 μW when operating at 24 MHz. With the help of the TDC, the ADPLL achieves 1.69-psrms jitter with a 24-MHz reference clock and a 1.8GHz output RF clock.