Extraction based verification method for off the shelf integrated circuits

Abstract

Off-the-shelf Integrated Circuits (ICs) are used in the design of many products. The IC is supposed to implement a set of available specifications describing the function of the IC. Users of off-the-shelf ICs need a simple and effective method to validate the specifications to insure that the IC implements exclusively the set of available specifications. In this paper, we propose an approach to validate these specifications by a set of IC re-engineering experiments. The proposed approach is based on the construction of a high-level description of the packaged IC and on using the extracted description to validate the specifications. The approach uses the scan operations (available for manufacturing test of the IC) and the IC specification to disassemble the states/flip-flops and output functions of the packaged IC. Using the disassembled functions, a Register Transfer Level (RTL) model suitable for Computer-Aided Design manipulation is constructed. The disassembling is based on an ATPG scan experiment. Information on the scan chains is employed to construct the connectivity of the logic function. The connectivity is then used to discover the implemented logic. Using the proposed approach, we re-constructed over 90% of the system functions for an example IC.