Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification

Abstract

Further compact-model development for LDMOS is reported, enabling concurrent device and circuit optimizations by only varying the ratio between gate-overlap length $(L_{\mathrm{o}\mathrm{v}\mathrm{e}\mathrm{r}})$ and resistive-drift length $(L_{\mathrm{drift}})$. Different from the conventional carrier-dynamics understanding within these two regions, LDMOS shows abnormal characteristics during such a ratio variation. The pinch-off condition occurs under the gate overlap region, and the pinch-off point is found to move along $L_{\mathrm{o}\mathrm{v}\mathrm{e}\mathrm{r}}$ with increased drain voltage, even under the accumulation condition. This means that carrier conductivity is no longer controlled by the gate voltage but by the drain voltage. The precise pinch-off condition is determined by the field balancing within gate-overlap and resistive-drift regions. The pinch-off length $(\Delta L)$ within $L_{\mathrm{o}\mathrm{v}\mathrm{e}\mathrm{r}}$ sustains $V_{\mathrm{ds}}$ together with $L_{\mathrm{drift}}$. Thus, the pinch-off region contributes as a part of $L_{\mathrm{drift}}$ and improves the device’s high-voltage applicability. A new model is developed to describe this balancing phenomenon analytically, where the key physical quantity is $\Delta L$. The developed $\Delta L$ model considers the potential distribution along $L_{\mathrm{o}\mathrm{v}\mathrm{e}\mathrm{r}}$ together with $L_{\mathrm{drift}}$. At the pinch-off point, the field induced by $V_{\mathrm{g}s}$ and that by $V_{\mathrm{ds}}$ are assumed to be equal, which derives an analytical description for $\Delta L$. Evaluation results with the developed model are verified with 2D-numerical-device-simulation results.