Exploration of digital latch design using ballistic deflection transistors — Modeling and simulation

Abstract

In this paper, we explore the feasibility of a digital latch design using ballistic deflection transistors (BDTs). An analytical model, based on Monte Carlo simulations for different sizes of BDTs, has been integrated into a behavioral Verilog A module to facilitate the investigation of digital latch design. The simulation results indicate interesting capability of latch operation by holding data in a stable operating state.