Z. Bao, S. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin
{"title":"A low cost, high quality embedded array DFT technique for high performance processors","authors":"Z. Bao, S. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin","doi":"10.1109/DELTA.2006.5","DOIUrl":null,"url":null,"abstract":"This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2006.5","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.
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