An on-chip NBTI monitor for estimating analog circuit degradation

Abstract

Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to digital switching and high packaging density of SoC) and constant DC bias there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous failure or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins or employing adaptive body bias/adaptive voltage scaling based calibration algorithms using on-chip sensors or monitors. We present an ultra low power and small area on-chip NBTI sensor which can be used for accurately sensing the NBTI degradation in analog circuits. We have shown that the temporal degradation in threshold voltage of pMOS transistor in analog circuits has high correlation to the variation of reference voltage of our NBTI sensor which can be exploited for accurate calibration of analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.