BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line

T. Schram, Q. Smets, M. Heyne, B. Graven, E. Kunnen, A. Thiam, K. Devriendt, A. Delabie, D. Lin, D. Chiappe, I. Asselberghs, M. Lux, S. Brus, C. Huyghebaert, S. Sayan, A. Juncker, M. Caymax, I. Radu
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引用次数: 7

Abstract

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.
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BEOL兼容WS2晶体管完全制造在一个300毫米的中导线
基于ws2的晶体管首次使用生产工具成功集成在300mm中试线上。采用区域选择性化学气相沉积(CVD)或原子层沉积(ALD)沉积二维材料。不需要材料转移。主要的集成挑战是有限的粘附性和少数单层二维材料的脆弱性。通过在湿法加工过程中使用牺牲的Al2O3封盖层和封装2D材料的边缘,可以避免这些问题。WS2通道与Ti/TiN侧触点和行业标准的后端线(BEOL)流接触。这种新颖的低温流为在BEOL中集成背控二维晶体管提供了前景。
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