Madhuri R A, Mahima M Hampali, Nisarga Umesh, P. S, Y. J. Shirur, V. S. Chakravarthi
{"title":"Design and Implementation of EDMA Controller for AI based DSP SoCs for Real- Time Multimedia Processing","authors":"Madhuri R A, Mahima M Hampali, Nisarga Umesh, P. S, Y. J. Shirur, V. S. Chakravarthi","doi":"10.1109/I-SMAC49090.2020.9243535","DOIUrl":null,"url":null,"abstract":"Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.","PeriodicalId":432766,"journal":{"name":"2020 Fourth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 Fourth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I-SMAC49090.2020.9243535","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.
在实时多媒体处理应用中,多数据流的处理需要高性能的多传输,使SoC (Processor System on Chips)系统不堪重负。高性能直接存储器访问(DMA)控制器在不需要处理器干预的情况下进行批量数据传输,减轻了处理器的负担。即使在大多数基于人工智能(AI)的系统和需要高速批量数据传输的通信系统中的交错功能中也是如此。这是通过设计增强型直接存储器访问(EDMA)控制器来实现的,用于高速批量数据传输。本文提出了一种增强型DMA核心的设计,该核心可用于基于人工智能的高性能数字信号处理SoC。EDMA核心用于灵活的内存访问和批量数据传输。EDMA核心支持在输入或输出(I/O)设备和核心处理单元之间进行数据传输的几种方法。SoC中的处理器用于编程DMA (Direct Memory Access)传输指令,实际传输由EDMA核心执行,不受处理器的干扰。EDMA设计支持灵活的寻址模式,如线性,循环,步进批量数据传输。EDMA核心计划在交错实时视频处理的实际应用场景中进行测试用例验证。