Reusable Architectures And Intellectual Property

Abstract

The papers in this section describe reusable architectures and address some of the important issues of intellectual property. The first paper presents soft cores for well-established industrystandard microcontrollers. The authors discuss the development effort, their verification strategy and the simulation environment as well as the IP difficulties encountered. The second paper focuses on a methodology for producing process portable hard cores using a cell based array architecture. The Cell Based Array Block Expert flow is presented that can be wed to automatically port IP cores so that they are optimally implemented in a target process.