Layout optimization of CMOS Interconnects for Heating, Cooling and Improved Stress Distribution

V. Hein, K. Weide-Zaage, Xi Yang
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Abstract

The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement.The simulations of the distribution of the temperature and the mechanical stress illustrates the important parameters and their interactions.The paper presents new ANSYS® -simulations on some exemplary heater layout variants in the highly robust metallization design. The scientific questions were the suitability and the benefits of such a heater layout for heating, cooling and stress distribution in CMOS circuits. Different heater-test line models have been analysed by ANSYS® -simulations. The variants of the models were forced or no forced current in heater and/or test line and the kind of metal layer of heater connection. The current density, temperature, their gradients, the hydrostatic stress, the Von Mises stress and the mass flux divergences have been analysed.Such simulations can be utilized to improve parts of circuits like chip corners, sensitive transistors, circuits on GaN-substrate, with TSVs or applications with 3D integration. The local temperature and stress management can be improved by the special metallization layout and the improvement can be supported by simulation data.
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用于加热、冷却和改善应力分布的CMOS互连布局优化
CMOS电路的可靠性受到电流密度、温度和机械应力等局部不均匀性的影响。材料错配、温度阶跃等加工和后处理源以及粘接、三维集成和扩展操作条件等外在源引起的机械应力与可靠性的关系越来越密切。它会影响互连的寿命性能,也会影响应力敏感晶体管等有源器件的功能。第一次模拟支持优化互连布局的开发工作,以提高电路的可靠性。评估从用于加速可靠性试验的高金属层自加热试验结构的加热器开发开始。它继续发展了一个高坚固的金属堆栈。在加热器和高鲁棒金属化试验结构上的模拟和试验表明了这种布局改进的优越性。通过对温度和机械应力分布的模拟,说明了重要参数及其相互作用。本文对高鲁棒化设计中一些典型的加热器布局变化进行了新的ANSYS®模拟。科学问题是这种加热器布局对CMOS电路的加热、冷却和应力分布的适用性和好处。利用ANSYS®-simulation对不同的加热器测试线模型进行了分析。型号的变化是加热器和/或测试线的强制或无强制电流以及加热器连接的金属层的种类。分析了电流密度、温度及其梯度、流体静力应力、冯米塞斯应力和质量通量散度。这种模拟可用于改进芯片角、敏感晶体管、gan衬底电路、tsv或3D集成应用等部分电路。特殊的金属化布置可以改善局部温度和应力管理,模拟数据可以为这种改善提供支持。
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