{"title":"A 1 Mb/s–40 Mb/s human body channel communication transceiver","authors":"Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin","doi":"10.1109/VLSI-DAT.2015.7114536","DOIUrl":null,"url":null,"abstract":"A high data rate, low-power, and large random jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC) is presented in this paper. Firstly, an investigation of human body channel characteristics from 1MHz to 80MHz is discussed. Then in the transmitter part, the proposed WBS transceiver uses a NRZI encoding scheme to transmit data. At the receiver part, a blind 7X oversampling clock and data recovery (CDR) circuit with the vote mechanism can effectively recover the data which distorted by the frequency drift and random noise from body antenna effects. The proposed WBS transceiver is implemented in a standard performance 90nm CMOS process, and the core area is 0.04 mm2. The supported data rate of the proposed WBS transceiver ranges from 1Mb/s to 40Mb/s. The power consumption is 1.94mW at 40Mb/s, and the bit energy is 0.0485 nJ/b.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114536","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A high data rate, low-power, and large random jitter tolerance wideband signaling (WBS) transceiver for human body channel communication (BCC) is presented in this paper. Firstly, an investigation of human body channel characteristics from 1MHz to 80MHz is discussed. Then in the transmitter part, the proposed WBS transceiver uses a NRZI encoding scheme to transmit data. At the receiver part, a blind 7X oversampling clock and data recovery (CDR) circuit with the vote mechanism can effectively recover the data which distorted by the frequency drift and random noise from body antenna effects. The proposed WBS transceiver is implemented in a standard performance 90nm CMOS process, and the core area is 0.04 mm2. The supported data rate of the proposed WBS transceiver ranges from 1Mb/s to 40Mb/s. The power consumption is 1.94mW at 40Mb/s, and the bit energy is 0.0485 nJ/b.