Energy-efficient logic and SRAM design: A case study

Abstract

This paper discusses energy-efficient design, both for logic and for memories. For datapaths which are controlled by dynamic energy, high energy-efficiency can be obtained by significantly reducing the supply voltage. However, simply lowering VDD does not automatically imply more energy-efficient operation for SRAM memories, as they are dominated by static leakage. This paper identifies which design methodologies can be employed to achieve high energy-efficiency. In particular, a JPEG encoder fabricated in a 40nm CMOS technology is used as a case study to determine the trade-offs, challenges and benefits of energy-efficient design.