Spin mosfets using ferromagnetic schottky barrier contacts for the source and drain

S. Sugahara, M. Tanaka
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The simplest and most feasible way to realize a spin MOSFET is to replace the source/drain material of an Schottky barrier (SB) MOSFET with a ferromagnetic metal that forms a ferromagnetic Schottky junction with the Si channel (Fig.l). In this paper, we present the theoretical analysis and experimental demonstration of spin MOSFETs using a ferromagnetic metal for the SB source/drain. Fig.1 shows the structure of our model device used in the calculations. Assuming the ballistic transport of spin-polarized carriers in the nanometer-scale channel, the device performance was theoretically analyzed. Solid and dashed curves in Fig. 2 show calculated drain currents IDP and IDAP as a function of drain bias VDs in the parallel and antiparallel magnetization configurations, respectively, where gate bias VGS varied from 0.0 to 1.0 V in steps of 0.2 V. When the relative magnetization configuration of the source/drain is parallel, the spin MOSFET shows a large output current comparable to that of high performance MOSFETs, indicating the high transcondactance of the spin MOSFET. The output current for small VDS conditions (less than the pinch-off voltage) can be reduced by changing the relative magnetization of the source/drain from the parallel to antiparallel configuration. Figs. 3 and 4 show magnetocurrent ratio Nc [=(IDP-IDAP)/IDAP] as a function of VDs and VGS, respectively. Nc falls with increasing VDs, but it is enhanced with increasing VGS. These phenomena can be rationalized by spin dependent transport similar to the tunneling magnetoresistance effect and the gate-induced enhancement of spin injection efficiency [1]. The SB height SB of the source/drain is important to obtain large output currents and also large Nc. IDP dramatically increases with decreasing S5B in comparison with IDAP, and thus Nc increases with decreasing B, as shown in Fig. 5. This means that IDP and Nc can simultaneously increase without any trade-off, which is important for spin-electronic integrated circuit applications. In order to demonstrate the transistor action of a spin MOSFET using a ferromagnetic metal for the SB source/drain, a prototypic spin MOSFET was fabricated by using ferromagnetic silicide Fe,-1Si,. A bottom-gate structure with a SOI substrate was employed for simplicity, where the buried oxide and the Si substrate were used as a gate dielectric and a gate electrode, respectively (Fig.6). The fabrication procedures are as follows: A p-type (001) SOI wafer with resistivity 10-20 Q-cm was used as a substrate. The SOI thickness was 50nm. The channel region was defined by using a sio2 hard mask, and then a 70-nm-thick Fe layer was deposited on the SOI surface by electron beam evaporation. Successively, Fe,-,Si, was formed by rapid thermal annealing (RTA) at 700C for 4 min in an N2 ambient. Finally, the mesa isolation of the device was done to define the active region. The physical gate length and width of the fabricated spin MOSFET were 1.6 gm and 10 gm, respectively (Fig.7). The fabricated Fe1 xSi,/Si junction showed clear Schottky diode characteristics, and it was found from preliminary experiments that the Schottky barrier height for p-type Si was estimated at less than 0.2 eV. Fig. 8 shows the output characteristics of the fabricated spin MOSFET, where gate bias VGS varied from 0 to 25 V in steps of 5 V. The output characteristics exhibited the inversion-channel mode operation of p-type FET. The accumulation-channel mode operation was also observed by the application of negative VGS and VDS. These results indicate that the fabricated spin MOSFET can operate as a SB MOSFET. The detailed characteristics including the magnetic transport properties of the fabricated spin MOSET will be presented at the conference. [1] S. Sugahara, to be published in LEE Proc. Circuits, Devices & Systems. [2] S. Sugahara and M. Tanaka, to be published in J. Appl. Phys. [3] S. Sugahara and M. Tanaka, Appl. Phys. Lett. 84 (2004) 2307.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. 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引用次数: 4

Abstract

Spin transistors, which utilize two ferromagnetic layers as a spin injector and as a spin detector, are very attractive as a basis for spin-electronic integrated circuits, owing to their additional spin degree of freedom in controlling output currents. In particular, recently proposed spin MOSFETs that are spin transistors analogous to MOSFETs are promising, since its prospected large current-drive capability, large magnetocurrent ratio, and compatibility with present MOS technology can lead to novel nonvolatile memory and reconfigurable logic architectures [1-3]. The spin MOSFETs can be classified by the structure of the source/drain and the source/drain material [1]. The simplest and most feasible way to realize a spin MOSFET is to replace the source/drain material of an Schottky barrier (SB) MOSFET with a ferromagnetic metal that forms a ferromagnetic Schottky junction with the Si channel (Fig.l). In this paper, we present the theoretical analysis and experimental demonstration of spin MOSFETs using a ferromagnetic metal for the SB source/drain. Fig.1 shows the structure of our model device used in the calculations. Assuming the ballistic transport of spin-polarized carriers in the nanometer-scale channel, the device performance was theoretically analyzed. Solid and dashed curves in Fig. 2 show calculated drain currents IDP and IDAP as a function of drain bias VDs in the parallel and antiparallel magnetization configurations, respectively, where gate bias VGS varied from 0.0 to 1.0 V in steps of 0.2 V. When the relative magnetization configuration of the source/drain is parallel, the spin MOSFET shows a large output current comparable to that of high performance MOSFETs, indicating the high transcondactance of the spin MOSFET. The output current for small VDS conditions (less than the pinch-off voltage) can be reduced by changing the relative magnetization of the source/drain from the parallel to antiparallel configuration. Figs. 3 and 4 show magnetocurrent ratio Nc [=(IDP-IDAP)/IDAP] as a function of VDs and VGS, respectively. Nc falls with increasing VDs, but it is enhanced with increasing VGS. These phenomena can be rationalized by spin dependent transport similar to the tunneling magnetoresistance effect and the gate-induced enhancement of spin injection efficiency [1]. The SB height SB of the source/drain is important to obtain large output currents and also large Nc. IDP dramatically increases with decreasing S5B in comparison with IDAP, and thus Nc increases with decreasing B, as shown in Fig. 5. This means that IDP and Nc can simultaneously increase without any trade-off, which is important for spin-electronic integrated circuit applications. In order to demonstrate the transistor action of a spin MOSFET using a ferromagnetic metal for the SB source/drain, a prototypic spin MOSFET was fabricated by using ferromagnetic silicide Fe,-1Si,. A bottom-gate structure with a SOI substrate was employed for simplicity, where the buried oxide and the Si substrate were used as a gate dielectric and a gate electrode, respectively (Fig.6). The fabrication procedures are as follows: A p-type (001) SOI wafer with resistivity 10-20 Q-cm was used as a substrate. The SOI thickness was 50nm. The channel region was defined by using a sio2 hard mask, and then a 70-nm-thick Fe layer was deposited on the SOI surface by electron beam evaporation. Successively, Fe,-,Si, was formed by rapid thermal annealing (RTA) at 700C for 4 min in an N2 ambient. Finally, the mesa isolation of the device was done to define the active region. The physical gate length and width of the fabricated spin MOSFET were 1.6 gm and 10 gm, respectively (Fig.7). The fabricated Fe1 xSi,/Si junction showed clear Schottky diode characteristics, and it was found from preliminary experiments that the Schottky barrier height for p-type Si was estimated at less than 0.2 eV. Fig. 8 shows the output characteristics of the fabricated spin MOSFET, where gate bias VGS varied from 0 to 25 V in steps of 5 V. The output characteristics exhibited the inversion-channel mode operation of p-type FET. The accumulation-channel mode operation was also observed by the application of negative VGS and VDS. These results indicate that the fabricated spin MOSFET can operate as a SB MOSFET. The detailed characteristics including the magnetic transport properties of the fabricated spin MOSET will be presented at the conference. [1] S. Sugahara, to be published in LEE Proc. Circuits, Devices & Systems. [2] S. Sugahara and M. Tanaka, to be published in J. Appl. Phys. [3] S. Sugahara and M. Tanaka, Appl. Phys. Lett. 84 (2004) 2307.
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自旋mosfet采用铁磁肖特基势垒触点作为源极和漏极
自旋晶体管利用两个铁磁层作为自旋注入器和自旋探测器,由于其在控制输出电流方面具有额外的自旋自由度,因此作为自旋电子集成电路的基础非常有吸引力。特别是,最近提出的自旋mosfet是一种类似于mosfet的自旋晶体管,由于其预期的大电流驱动能力,大磁流比,以及与现有MOS技术的兼容性,可以导致新的非易失性存储器和可重构逻辑架构[1-3]。自旋mosfet可根据源极/漏极结构和源极/漏极材料进行分类[1]。实现自旋MOSFET的最简单和最可行的方法是用铁磁性金属取代肖特基势垒(SB) MOSFET的源极/漏极材料,与Si沟道形成铁磁性肖特基结(图1)。本文对自旋mosfet进行了理论分析和实验证明,该器件采用铁磁金属作为SB源极/漏极。图1显示了我们在计算中使用的模型装置的结构。假设自旋极化载流子在纳米尺度通道内的弹道输运,对器件性能进行了理论分析。图2中的实线和虚线分别显示了平行和反平行磁化配置下计算漏极电流IDP和IDAP作为漏极偏置VDs的函数,其中栅极偏置VGS以0.2 V的阶跃从0.0到1.0 V变化。当源极/漏极的相对磁化配置为并联时,自旋MOSFET显示出与高性能MOSFET相当的大输出电流,这表明自旋MOSFET具有高跨电性。小VDS条件下的输出电流(小于引脚电压)可以通过将源极/漏极的相对磁化强度从并联改变为反并联来减小。图3和图4分别显示了磁流比Nc [=(IDP-IDAP)/IDAP]与VDs和VGS的关系。Nc随VDs的增加而下降,但随VGS的增加而增强。这些现象可以通过类似于隧道磁阻效应的自旋相关输运和栅极诱导的自旋注入效率增强来合理化[1]。源极/漏极的SB高度SB对于获得大输出电流和大Nc非常重要。与IDAP相比,IDP随着S5B的减小而急剧增大,因此Nc随着B的减小而增大,如图5所示。这意味着IDP和Nc可以同时增加而没有任何权衡,这对于自旋电子集成电路应用非常重要。为了证明使用铁磁性金属作为SB源极/漏极的自旋MOSFET的晶体管作用,用铁磁性硅化物Fe,-1Si,制作了一个自旋MOSFET的原型。为了简单起见,采用了带有SOI衬底的底栅结构,其中埋藏的氧化物和Si衬底分别用作栅极电介质和栅极电极(图6)。采用电阻率为10-20 Q-cm的p型(001)SOI晶圆作为衬底。SOI厚度为50nm。利用sio2硬掩膜确定通道区域,然后通过电子束蒸发在SOI表面沉积70 nm厚的Fe层。通过快速退火(RTA),在N2环境下,在700C下加热4min,形成Fe,-,Si。最后,对器件进行了台面隔离,确定了有源区域。制备的自旋MOSFET的物理栅长和宽度分别为1.6 gm和10 gm(图7)。制备的Fe1 xSi,/Si结具有明显的肖特基二极管特性,初步实验发现p型Si的肖特基势垒高度估计小于0.2 eV。图8显示了制作的自旋MOSFET的输出特性,其中栅极偏置VGS以5 V的阶跃从0到25 V变化。输出特性表现为p型场效应管的反沟道模式工作。应用负VGS和VDS也观察到积累通道模式的运作。这些结果表明所制备的自旋MOSFET可以作为SB型MOSFET工作。在本次会议上,我们将详细介绍所制备的自旋MOSET的磁性输运特性。[1]李志刚,《电路、器件与系统》。[2]杨志刚,《中国农业科学》。理论物理。[3]陈志强,陈志强。理论物理。Lett. 84(2004) 2307。
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