Fully Integrated Ultra-Wideband Differential Circulator Based on Sequentially Switched Delay Line in 28-nm FDSOI CMOS

J. Hwang, Byung-Wook Min
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引用次数: 1

Abstract

In this paper, a non-magnetic circulator, which realizes non-reciprocal signal flows by sequentially switching delay lines, is presented in 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The proposed circulator is designed differentially to increase power handling capability and bandwidth. The bandwidth of insertion loss and isolation can be extended by latticely coupled inductors used in the differential synthetic delay lines. The characteristic impedance of the delay lines is determined by considering the channel resistance of CMOS transistor. The measured insertion losses of transmitter (TX) to antenna (ANT) and ANT to receiver (RX) are 2.5 dB and 2.6 dB, respectively. TX to RX isolation is $> 20\ \text{dB}$ up to 7 GHz. The measured TX input power 1 dB compression point is 4.7 dBm at 3.5 GHz. The chip size of the differential circulator is $1.33\times 0.72\ \text{mm}^{2}$, which is as small as a single ended version, thanks to the coupled inductors.
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基于顺序开关延迟线的28纳米FDSOI CMOS全集成超宽带差分环行器
本文提出了一种基于28纳米全耗尽绝缘体上硅(FDSOI) CMOS工艺的非磁性环行器,该环行器通过顺序开关延迟线实现非互易信号流。所提出的环行器设计不同,以增加功率处理能力和带宽。差分合成延迟线采用晶格耦合电感可以提高插入损耗和隔离带宽。通过考虑CMOS晶体管的沟道电阻来确定延迟线的特性阻抗。测量到的发射机(TX)到天线(ANT)和天线(ANT)到接收机(RX)的插入损耗分别为2.5 dB和2.6 dB。TX到RX的隔离度$> 20\ \text{dB}$高达7 GHz。实测的TX输入功率1db压缩点在3.5 GHz时为4.7 dBm。差分环行器的芯片尺寸为$1.33\ × 0.72\ \text{mm}^{2}$,由于采用了耦合电感,因此与单端环行器一样小。
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