Transforming sequential logic in digital CMOS ICs for voltage and I/sub DDQ/ testing

Abstract

To ensure the functionality, quality and reliability of digital CMOS ICs, the conventional logic testing and I/sub DDQ/ testing are recognized as absolute test requirements. However, some of the bridging defects in sequential circuits are not detected by I/sub DDQ/. Furthermore, for complex devices, even scan based logic testing can be expensive. In this paper, a new concept of transforming sequential logic into purely combinational logic is described. With the help of the proposed method complete sequential logic is voltage and I/sub DDQ/ tested in four test vectors.<>