S. DasGupta, M. Graf, R. A. Rasmussen, R. Walther, T. Williams
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引用次数: 7
Abstract
This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.
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