Tag skipping technique using WTS buffer for optimal low power cache design

Abstract

In this paper we present a robust technique to reduce the power consumption for a 4-way set-associativity cache. Our algorithm is a modification of the technique proposed by H. Choi et al. (2000) which allows skipping tag look-ups to achieve a better power consumption design. Previous work shows that implementing tag-skipping technique on a Not-Load-on-write-miss architecture, though reduces the overall power consumption, yet still consumes significant power in write miss by frequently accessing main memory. We propose the use of a write tag-skipping (WTS) buffer (WTSB) to reduce the number of write misses by 50-85% therefore reducing accesses to more power consuming devices such as main memory. This results in shifting all tag-skipping operations occurring during a miss to a hit.