Parallel Algorithms for FIR Computation Mapped to ESCA Architecture

Abstract

IN this paper we present a parallel algorithm for FIR (Finite Impulse Response) filter computation based on Engineering and Scientific Computation Accelerator (ESCA) System. ESCA is a heterogeneous multi-core architecture aiming to accelerate the compute-intensive parallel computing in high performance applications. By taking advantage of SIMD processing elements (PEs) and hierarchical on-chip networks with high-bandwidth and low-latency inside ESCA, we can get a good performance at parallel computation, and find a way to implement the FIR kernel. By translating the FIR computation into Matrix-Vector multiplication, we proposed an improved implementation of FIR algorithm, which achieved higher performance.