Approximate Multiplier Architectures for Error Resilient Applications

Abstract

Approximate computing is an emerging paradigm to achieve substantial improvement in the area, speed, and power in image processing applications where exact computation is not required. This paper proposes new approximate unsigned multiplier architectures which aim to reduce the power consumption and area with better accuracy. For the 8-bit multiplier scheme, experimental results show an improvement of 41.4% and 34.02% in power and area respectively, when the proposed design is compared against the exact design, and 22.88% and 26.72% respectively when compared against other approximate designs, without compromising on the accuracy.