M. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, W. Craig
{"title":"Latchup in CMOS technology","authors":"M. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, W. Craig","doi":"10.1109/RELPHY.1998.670561","DOIUrl":null,"url":null,"abstract":"This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.","PeriodicalId":196556,"journal":{"name":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"62","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.1998.670561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 62
Abstract
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.
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