An efficient algorithm-based fault tolerance design using extended rearranged Hamming checksum

Abstract

Fault tolerance has been an important issue for systems involving intensive computations using a large number of processing elements. To effectively tolerate operation time faults in the systems, algorithm-based fault tolerance designs have been developed. Extended rearranged Hamming checksum scheme is proposed as an algorithm-based fault tolerance design. It is based on the rearranged Hamming checksum code with newly introduced negative elements in the checksum matrix. The overflow and round-off error probability of the scheme are greatly reduced compared to earlier designs, while both time latency and hardware overheads are small. Two important matrix computations are selected to show how the scheme works. Performance of the proposed design is evaluated and compared with those of existing schemes through computer simulation.<>