A new network processor architecture for high-speed communications

Abstract

Many applications require high-speed communications. To provide protocol processing with efficient hardware and software the use of a flexible and efficient platform becomes very important for high-speed communications networks. In this paper we first describe a top-level view of the implementations platform for handling communication protocols. From the top-level view we derived the requirements on a network processor (NP) which will be particularly useful for high-speed communications devices. To this end an efficient NP architecture is designed and implemented to meet the requirements. The key features of such a NP are bit field instructions, port-based instructions and the zero-latency task switch among others.