{"title":"Design and simulation of a high performance rail-to-rail CMOS op-amp at /spl plusmn/3V supply","authors":"M. Bhaskaran, S. Sriram, A. Stojcevski, A. Zayegh","doi":"10.1109/DELTA.2006.30","DOIUrl":null,"url":null,"abstract":"The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2006.30","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.
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