Design of Data Compression Mechanism in Cache Memory of Elbrus Processors

Abstract

Higher capacity of cache memory increases Hit Rate at the cost of power consumption and die area. Hardware data compression in cache allows increasing its effective capacity without significant negative effects on these characteristics. This work discusses the realization of data compression in L3 cache memory of modern processors with “Elbrus” architecture. One of the most efficient and at the same time fast compression algorithms is BDI (Base-Delta-Immediate) algorithm. Its modification, called BDI*-HL (Base-Delta-Immediate Modified, Half-Line), is selected for implementation. To achieve an increase in effective capacity, the principles of joint placement of compressed cache lines are introduced and implemented. L3 cache memory is modified to correctly work with compressed lines. A testing bench is developed to evaluate the effectiveness of the designed mechanism. The developed solution does not require any significant changes in the structure of cache memory, does not affect the principles of eviction policy and the coherency protocol and does not change values of working frequency and cache die area.