I/O supply current synthesis for power integrity analysis of single-ended signaling scheme

Abstract

The simultaneous switching noise (SSN) from single-ended signaling I/O interfaces is significant when there are multiple channels transmitting data in parallel. The memory interfaces use the single-ended signaling scheme where the power delivery noise spectrum may coincide with some critical radio bands or resonance frequencies within the platform depending on the bit pattern being transmitted from the driver buffers. This will adversely affect the timing margin and can be one of the electromagnetic interference (EMI) sources as well. While it is good to use transistor buffer models in SSN estimation, it may significantly increase the complexity resulting in too long simulation time or convergence problems. The suggested method takes the transient supply currents when the transistor buffer transits its state from 0 to 1 and from 1 to 0, and synthesizes the full supply current for an arbitrary bit-pattern and data rate. This allows high accuracy in the supply current profiles while minimizing the power integrity simulation complexity. The method is extendable to tri-state buffers and different channel termination schemes.