Area efficient BCD adder in Quantum dot Cellular Automata

B. Ramesh, M. Asharani, V. Srujana, P. Chaithanya, U. Rajaiah
{"title":"Area efficient BCD adder in Quantum dot Cellular Automata","authors":"B. Ramesh, M. Asharani, V. Srujana, P. Chaithanya, U. Rajaiah","doi":"10.1109/IC3I.2016.7917955","DOIUrl":null,"url":null,"abstract":"Quantum dot Cellular Automata (QCA) is one of the emerging technologies for implementing the combinational and sequential circuits. From the past few decades CMOS technology is being used in IC industry. But CMOS technology having certain limitations like high power, low-speed, switching losses etc, to overcome these limitations and to meet the requirements of the industry parameters QCA is used. Adder is the basic building block to perform arithmetic and logical operations. In this paper QCA based BCD adder is designed with less number of Quantum cells. By reducing the QCA cells improvement in the circuit parameters like frequency, area and power consumption. To implement BCD adder 3-input majority gate and inverter is used with different clock inputs.","PeriodicalId":305971,"journal":{"name":"2016 2nd International Conference on Contemporary Computing and Informatics (IC3I)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 2nd International Conference on Contemporary Computing and Informatics (IC3I)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IC3I.2016.7917955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

Quantum dot Cellular Automata (QCA) is one of the emerging technologies for implementing the combinational and sequential circuits. From the past few decades CMOS technology is being used in IC industry. But CMOS technology having certain limitations like high power, low-speed, switching losses etc, to overcome these limitations and to meet the requirements of the industry parameters QCA is used. Adder is the basic building block to perform arithmetic and logical operations. In this paper QCA based BCD adder is designed with less number of Quantum cells. By reducing the QCA cells improvement in the circuit parameters like frequency, area and power consumption. To implement BCD adder 3-input majority gate and inverter is used with different clock inputs.
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量子点元胞自动机中面积高效BCD加法器
量子点元胞自动机(QCA)是实现组合和顺序电路的新兴技术之一。从过去的几十年开始,CMOS技术被应用于集成电路行业。但是CMOS技术具有高功率、低速度、开关损耗等局限性,为了克服这些局限性,满足工业参数的要求,采用了QCA。加法器是执行算术和逻辑运算的基本构件。本文设计了基于QCA的BCD加法器,采用较少的量子单元。通过减少QCA单元,改善电路参数,如频率,面积和功耗。为了实现BCD加法器,采用三输入多数门和不同时钟输入的逆变器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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