B. Ramesh, M. Asharani, V. Srujana, P. Chaithanya, U. Rajaiah
{"title":"Area efficient BCD adder in Quantum dot Cellular Automata","authors":"B. Ramesh, M. Asharani, V. Srujana, P. Chaithanya, U. Rajaiah","doi":"10.1109/IC3I.2016.7917955","DOIUrl":null,"url":null,"abstract":"Quantum dot Cellular Automata (QCA) is one of the emerging technologies for implementing the combinational and sequential circuits. From the past few decades CMOS technology is being used in IC industry. But CMOS technology having certain limitations like high power, low-speed, switching losses etc, to overcome these limitations and to meet the requirements of the industry parameters QCA is used. Adder is the basic building block to perform arithmetic and logical operations. In this paper QCA based BCD adder is designed with less number of Quantum cells. By reducing the QCA cells improvement in the circuit parameters like frequency, area and power consumption. To implement BCD adder 3-input majority gate and inverter is used with different clock inputs.","PeriodicalId":305971,"journal":{"name":"2016 2nd International Conference on Contemporary Computing and Informatics (IC3I)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 2nd International Conference on Contemporary Computing and Informatics (IC3I)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IC3I.2016.7917955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Quantum dot Cellular Automata (QCA) is one of the emerging technologies for implementing the combinational and sequential circuits. From the past few decades CMOS technology is being used in IC industry. But CMOS technology having certain limitations like high power, low-speed, switching losses etc, to overcome these limitations and to meet the requirements of the industry parameters QCA is used. Adder is the basic building block to perform arithmetic and logical operations. In this paper QCA based BCD adder is designed with less number of Quantum cells. By reducing the QCA cells improvement in the circuit parameters like frequency, area and power consumption. To implement BCD adder 3-input majority gate and inverter is used with different clock inputs.