Use of switched buffers in very high-speed data converters

Abstract

We present a new design approach for high resolution analog-to-digital converters operating at very high speeds. We show that using CMOS switches and the switched current technique are not convenient for advanced specifications. The switched buffer method proposed here offers new perspectives since it allows the designer to preserve accuracy even at high speeds of operation. The switched buffer consists of a bipolar high-speed unity gain amplifier controlled by a clock phase which allows the buffered output node to be turned into high impedance. We demonstrate the usability of switched buffers in a pipeline architecture and in a sigma delta modulator. Simulation results show that the circuits can operate at 200 MHz and 500 MHz respectively with an expected resolution better than 13-14 bit.