Dictionary-based program compression on TTAs: effects on area and power consumption

Abstract

Program code size has become a critical design constraint of embedded systems. Large program codes result in large memories, which increase the size and cost of the chip. Poor code density is a problem especially in VLIW architectures, where a long instruction word is used to control the concurrently operating hardware resources. In addition, wide instructions increase the memory bandwidth, which may result in increased power consumption. Dictionary compression is one of the most often used compression methods to improve the code density due to its simplicity. In this paper, dictionary-based program compression is applied on transport triggered architecture, a customizable processor architecture that is particularly suitable for tailoring the hardware resources according to the requirements of the application. The effects on area and power consumption were measured. We observed that at best, the area of the instruction memory and the fetch and decode logic could be reduced by 87%, and power consumption by 80%, correspondingly.