U. Kwon, T. Okagaki, Young-seok Song, Sungyeol Kim, Yohan Kim, Minkyoung Kim, A. Kim, Saetbyeol Ahn, Jihye Shin, Yonghee Park, Jongchol Kim, D. Kim, Weiyi Qi, Yang Lu, Nuo Xu, Hong-hyun Park, J. Wang, W. Choi
{"title":"Intelligent DTCO (iDTCO) for next generation logic path-finding","authors":"U. Kwon, T. Okagaki, Young-seok Song, Sungyeol Kim, Yohan Kim, Minkyoung Kim, A. Kim, Saetbyeol Ahn, Jihye Shin, Yonghee Park, Jongchol Kim, D. Kim, Weiyi Qi, Yang Lu, Nuo Xu, Hong-hyun Park, J. Wang, W. Choi","doi":"10.1109/SISPAD.2018.8551723","DOIUrl":null,"url":null,"abstract":"Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\\sim$10 times with good accuracy of >95%.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2018.8551723","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$\sim$10 times with good accuracy of >95%.
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