Testing for path delay faults using test points

Abstract

Path delay fault testing is often difficult due to the large number of paths that must be tested. Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of paths that need to be tested in a circuit. Test points allow the tester to test subpaths of the circuit and then draw conclusions of the operability of the circuit based upon the delays of subpaths. We illustrate some of the limitations of current subpath testing procedures and illustrate some of the difficulties associated with unstructured test point placement. We give an implementation of test points embedded in a scan chain and present a new testing technique that is more accurate than the previous method. We also present a novel test point insertion approach that has reasonable test times and minimal impact on the hardware size and the operational clock.