A fuzzy logic inference processor

Symposium 1993 on VLSI Circuits Pub Date : 1993-05-19 DOI:10.1109/VLSIC.1993.920526

J. Fattaruso, S. Mahant-Shetti, J. B. Barton

引用次数: 47

Abstract

This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm by 10 mm in a 0.8 /spl mu/m CMOS technology, and is currently undergoing preliminary testing.

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一种模糊逻辑推理处理器

该模数混合模糊逻辑推理处理器芯片在32条规则的知识库上并行计算推理结果。模拟预测该阵列的计算时间约为2 /spl mu/sec。处理器接口的行为类似于静态RAM，但内部计算在模拟域中执行，预期精度为6位。完成的芯片尺寸为7mm × 10mm，采用0.8 /spl μ m CMOS技术，目前正在进行初步测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Symposium 1993 on VLSI Circuits

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