Design and Verification of AMBA AHB

Abstract

The AHB (Advanced High-performance Bus) is a high-performance bus in AMBA (Advanced Microcontroller Bus Architecture) family. It is a standard for intercommunication of modules in a system. AHB standards are defined by ARM and supports the communication of on-chip memories processors and interfaces of off-chip external memory. In this paper we present, design and perform verification of AHB which support one master and four slaves. In this work, the design of the AHB Protocol is developed comprising of the basic blocks such as Master, Slave, decoder and multiplexers. This AMBA-AHB protocol can be used in any application provided the design should be an AHB compliant. The building blocks of the design master, slaves, decoder and multiplexers are developed in Verilog. The verification environment is developed in system Verilog (SV). QuestaSim (Advanced verification tool from Mentor Graphics) is used to simulate and verify the design and calculate code and functional coverages.