Junjie Gu, Haoqi Qin, Guixiang Jin, Hao Xu, Weitian Liu, T. Han, Mi Tian, Weiqiang Zhu, Na Yan
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引用次数: 1
Abstract
In this paper, a series-parallel combined Doherty power amplifier is proposed. The Doherty architecture is adopted for PBO efficiency enhancement. The power-combining structure is applied for the improvement of saturated output power. The PA is designed in a 40nm bulk CMOS process to achieve a saturated output power of 23dBm and a peak power-added efficiency of 40%. The 6-dB back-off power-added efficiency achieves 26%, indicating obvious efficiency improvement owing to Doherty architecture. The 3-dB bandwidth of the proposed power amplifier is over 6GHz, and OP1dB exceeds 20 dBm in 25–31 GHz.
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