IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy

Yu Wei P'ng, Moo Kit Lee, P. W. Ng, Chin Hu Ong
{"title":"IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy","authors":"Yu Wei P'ng, Moo Kit Lee, P. W. Ng, Chin Hu Ong","doi":"10.1109/ATS.2007.36","DOIUrl":null,"url":null,"abstract":"The implementation of IDDQ test is increasingly challenging with the shrinking of process geometry in nanotechnologies. This paper presents a case study of the test challenges that the industry is facing in deep submicron process. An IDDQ manufacturing test strategy is discussed to address the challenges.","PeriodicalId":289969,"journal":{"name":"16th Asian Test Symposium (ATS 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th Asian Test Symposium (ATS 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2007.36","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

The implementation of IDDQ test is increasingly challenging with the shrinking of process geometry in nanotechnologies. This paper presents a case study of the test challenges that the industry is facing in deep submicron process. An IDDQ manufacturing test strategy is discussed to address the challenges.
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纳米技术中的IDDQ测试挑战:制造测试策略
随着纳米技术中工艺几何尺寸的不断缩小,IDDQ测试的实施越来越具有挑战性。本文介绍了深亚微米工艺在测试中面临的挑战。讨论了IDDQ制造测试策略来解决这些挑战。
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