Impact Analysis of Dual Material Double Gate Oxide-Stack Junction-Less MOSFET in RFID Memory Cell Realisation

Dipanjan Sen, Savio Jay Sengupta, Subhashis Roy, Sudhabindu Ray, S. Sarkar
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Abstract

In this proposed article, a realization of RFID memory cell has been performed using Dual Material Double Gate Stack-Oxide Junction-Less MOSFET for high speed and low power application [1] in Sub-threshold regime. SNM, Power and Delay of the Memory Cell or SRAM circuit in different operating modes have been analyzed in depth. Dual Material Double Gate Oxide-Stack Junction-Less MOSFET (DMDGS-JLT) shows promising $\mathrm{I}_\mathrm{ON}/\mathrm{I}_\mathrm{OFF}$ ratio, less subthreshold swing and less Drain Induced Barrier Lowering or DIBL, in comparison with Double Gate Junction-Less MOSFET. So, proposed SRAM cell would be efficacious to offer less power dissipation and higher speed and a better Static Noise Margin. The impact of DMDGS-JLT in realizing RFID memory cell or SRAM has been studied in sub-threshold regime for ultra-low power tag design. Extensive simulations are performed using SILVACO ATLAS platform to validate the analyzed models. Besides, an optimum supply voltage range has been chosen to get an ultra-low power and higher speed of operation. DMDGS-JLT can be an alternative for ultra-low power Passive-RFID tag design, which results into greater time-span of the battery.
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双材料双栅无氧化堆结MOSFET在RFID存储单元实现中的影响分析
在本文中,采用双材料双栅堆叠无结MOSFET实现了RFID存储单元,用于亚阈值状态下的高速低功耗应用[1]。深入分析了SRAM电路在不同工作模式下的SNM、功率和时延。与双栅无结MOSFET相比,双材料双栅无氧化层结MOSFET (DMDGS-JLT)表现出良好的$\ mathm {I}_\ mathm {ON}/\ mathm {I}_\ mathm {OFF}$比值,更小的亚阈值摆幅和更少的漏极诱导势垒降低(DIBL)。因此,所提出的SRAM单元将有效地提供更低的功耗,更高的速度和更好的静态噪声裕度。在超低功耗标签设计的亚阈值条件下,研究了DMDGS-JLT对实现RFID存储单元或SRAM的影响。利用SILVACO ATLAS平台进行了大量的仿真,以验证分析的模型。此外,还选择了最佳的电源电压范围,以获得超低功耗和较高的运行速度。DMDGS-JLT可以作为超低功耗无源rfid标签设计的替代方案,从而延长电池的使用时间。
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