Data path tradeoffs using MABAL

Abstract

A set of novel tradeoff experiments using MABAL, a module and bus allocation program, is described. MABAL uses a simple heuristic algorithm to concurrently perform functional unit allocation, register allocation, interconnect allocation, and module binding, while minimizing overall cost. MABAL was used to produce over 3000-RTL (register transfer level) designs from a specification which had been previously scheduled. Tradeoffs between buses and multiplexers and between data steering logic and functional logic were investigated. The results indicate that data path tradeoffs were sensitive to the characteristics of the module library used, and illustrate the difficulty of integrating module generations or logic synthesis, with high-level synthesis.<>